The present invention relates to semiconductor device technologies and in particular to a technology effectively applicable to a semiconductor device having a nonvolatile memory cell.
One of storage devices (memories) provided in semiconductor devices is nonvolatile memory. This is a memory that holds memory information even after power supply is turned off and nonvolatile memories include ROM (Read Only Memory), Flash memory, phase-change memory, and the like.
Among the above-mentioned nonvolatile memories, there is an element that stores electric charges, such as electrons, in a conductor film in floating state and thereby stores information. As an example, it will be assumed that a field effect transistor (also referred to as FET) with an MIS (Metal Insulator Semiconductor) structure (hereafter, simply referred to as MIS transistor) having a conductor film in floating state as a gate electrode is configured. In this case, the state of electric charges of this floating gate electrode manifests itself as change in threshold voltage. Thus the state of memory can be read from the drain current of an MIS transistor or the like. Electric charges accumulated in a floating gate electrode are less prone to leak to outside and thus information can be held without the supply of power.
Among nonvolatile memories having such a floating gate electrode, there is a nonvolatile memory whose floating gate electrode is formed by the same process as for the gate electrode of another MIS transistor. This facilitates manufacturing processes and the fabrication yield and the reliability of semiconductor devices having a nonvolatile memory are enhanced. The structure of this floating gate electrode of a nonvolatile memory is comprised of a single-layer conductor film similarly with ordinary MIS transistors. Control of an electric field for injecting electric charges into a floating gate electrode is carried out by, for example, the coupling capacitance between a well formed in a substrate and the floating gate electrode or the like.
For example, Japanese Unexamined Patent Publication No. 2004-253685 (Patent Document 1) discloses EEPROM (Electrically Erasable Programmable ROM) including a single-layer polysilicon floating gate of P conductivity type.    [Patent Document 1] Japanese Unexamined Patent Publication No. 2004-253685